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ASAHI KASEI
[AK4520A]
AK4520A
100dB 20Bit Stereo ADC & DAC
General Description The AK4520 is a stereo CMOS A/D & D/A converter for middle-range MD/DAT, Surround System and musical instruments. Signal inputs and outputs are single-ended. The DAC outputs are analog filtered to remove out of band noise. External components are minimized. Features
Stereo ADC - 64x Oversampling - S/(N+D): 90dB at 5V, 86dB at 3V - Dynamic Range: 100dB at 5V, 96dB at 3V - S/N: 100dB at 5V, 96dB at 3V - Digital HPF for offset cancel Stereo DAC - 128x Oversampling - 2nd order SCF + 2nd order CTF - Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling - S/(N+D): 90dB at 5V, 90dB at 3V - Dynamic Range: 100dB at 5V, 96dB at 3V - S/N: 100dB at 5V, 96dB at 3V High Jitter Tolerance Sample Rate Ranging from 16kHz to 54kHz Master Clock: 256fs or 384fs 2.7 to 3.6V or 4.5 to 5.5V supply Low Power Dissipation: 255mW Small 28pin VSOP Package
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ASAHI KASEI Ordering Guide AK4520A-VF AKD4520 -10+70C 28pin VSOP AK4520A Evaluation Board
[AK4520A]
Pin Layout
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ASAHI KASEI
[AK4520A]
PIN/FUNCTION No. 1 Pin Name VREFH I/O I Function Positive Voltage Reference Input Pin, VA Used as a positive voltage reference by ADC & DAC. VREFH is connected externally to filtered VA. Negative Voltage Reference Input Pin, AGND Used as a negative voltage reference by ADC & DAC. VREFL is connected externally to AGND. Rch Analog Positive Input pin Rch Analog Negative Input Pin Lch Analog Positive Input pin Lch Analog Negative Input Pin Analog Power Supply Pin Analog Ground pin Audio Data Interface Format Pin Audio Data Interface Format Pin Input/Output Channel Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Audio Serial Data Output Pin Master Clock Input Pin De-emphasis Frequency Select Pin De-emphasis Frequency Select Pin Test Pins (Pull down pins) Must be left open or connected to DGND. Digital Power Supply Pin Digital Ground Pin DAC Power-Down Mode Pin ADC Power-Down Mode Pin Master Clock Select Pin "H": 384fs, "L": 256fs Lch analog output pin Rch analog output pin Common Voltage Output Pin, VA/2
2
VREFL
I
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
AINR+ AINRAINL+ AINLVA AGND DIF0 DIF1 LRCK SCLK SDTI SDTO MCLK DEM0 DEM1 TST3 TST2 TST1 VD DGND PWDA PWAD CMODE AOUTL AOUTR VCOM
I I I I I I I I I O I I I I/O I/O I I I I O O O
Note: All input pins except pull-down pins should not be left floating.
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ASAHI KASEI
[AK4520A]
ABSOLUTE MAXIMUM RATINGS (AGND,DGND=0V; Note 1 ) Parameter Analog Digital |AGND-DGND| Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature (power applied) Storage Temperature Note: 1 . All voltages with respect to ground. Power Supplies: Symbol VA VD GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 0.3 10 VA+0.3 VD+0.3 70 150 Units V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND,DGND=0V; Note 1 ) Parameter Power Supplies: (Note 2 ) 3V operation Analog Digital Symbol VA VD min 2.7 2.7 typ 3.0 3.0 5.0 5.0 max 3.6 VA 5.5 VA Units V V V V
5V operation Analog VA 4.5 Digital VD 4.5 Note: 1 . All voltages with respect to ground. 2 . The power up sequence between VA and VD is not critical.
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ASAHI KASEI
[AK4520A]
ANALOG CHARACTERISTICS (Ta=25C; VA,VD=5.0V; AGND=DGND=0V; VREFH=VA; VREFL=AGND; fs=44.1kHz; SCLK=64fs, Signal Frequency=1kHz; 20bit Data; Measurement frequency=10Hz20kHz; unless otherwise specified) Parameter min typ max ADC Analog Input Characteristics: Differential Inputs; Analog Source Impedance=470 Resolution S/(N+D) (-0.5dB Input) 20 80 84 90 94 90 94 90 86 90 96 100 96 100 110 0.1 20 1.8 3.0 30 50 VA=3V (Note 3 ) VA=5V DR (-60dB Input, A-Weighted) VA=3V (Note 4 ) VA=5V S/N (A-Weighted) VA=3V (Note 4 ,5 ) VA=5V Interchannel Isolation Interchannel Gain Mismatch Gain Drift Input Voltage VA=3V AIN=0.6x(VREFH-VREFL) VA=5V Input Resistance Power Supply Rejection (Note 6 ) DAC Analog Output Characteristics: Resolution S/(N+D) 20 VA=3V VA=5V VA=3V VA=5V VA=3V VA=5V 84 80 92 96 92 96 90 90 90 96 100 96 100 110 0.1 20 1.88 3.13 Bits dB dB dB dB dB dB dB dB ppm/C Units Bits dB dB dB dB dB dB dB dB ppm/C Vpp Vpp k dB
0.3 1.9 3.15
1.7 2.85 20
DR (-60dB Output, A-Weighted) (Note 4 ) S/N (A-Weighted) (Note 7,5 ) Interchannel Isolation Interchannel Gain Mismatch 0.3 Gain Drift Output Voltage VA=3V 1.76 1.99 Vpp AOUT=0.626x(VREFH-VREFL) VA=5V 2.94 3.32 Vpp k Load Resistance 10 Load Capacitance 25 pF Power Supply Rejection (Note 6 ) 50 dB Note: 3 . In case of single ended input, S/(N+D)=84dB(typ, @VA=5V). 4 . In case of 16bit, DR and S/N of ADC are 98dB. DR of DAC is 98dB. 5 . S/N measured by CCIR-ARM is 96dB at each converter and 94dB at ADC to DAC loopback. 6 . PSR is applied to VA,VD with 1kHz, 50mVpp. VREFH/VREFL pin is held a constant voltage. 7 . As the input data is "0", S/N is 100dB regardless of resolution.
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ASAHI KASEI
[AK4520A]
Parameter
min
typ
max
Units
Power supply Current VA=VD=5V mA 62 41 PWAD="H",PWDA="H" Analog AD+DA mA 26 17 PWAD="H",PWDA="L" VA AD mA 38 25 PWAD="L",PWDA="H" DA Digital AD+DA PWAD="H",PWDA="H" 10 15 mA VD AD PWAD="H",PWDA="L" 6 9 mA (Note 8 ) DA PWAD="L",PWDA="H" 4 6 mA VA+VD Power down PWAD="L",PWDA="L" 0.2 0.4 mA Note:8 The typical supply current of VD drops to AD+DA=5.5mA, AD=3.5mA, DA=2mA at 3.0V supply voltage. FILTER CHARACTERISTICS (Ta=25C; VA,VD=2.75.5V; fs=44.1kHz; DEM0="1", DEM1="0") Parameter ADC Digital Filter(Decimation LPF): Passband (Note 9 ) -0.005dB -0.02dB -0.06dB -6.0dB PB 0 0 0 0 24.34 80 29.3 0 0.9 2.7 6.0 0 0 24.1 43 14.7 20.0 22.05 0.06 19.76 20.02 20.20 22.05 0.005 kHz kHz kHz kHz kHz dB dB 1/fs us Hz Hz Hz kHz kHz kHz dB dB 1/fs Symbol min typ max Units
Stopband Passband Ripple Stopband Attenuation Group Delay (Note 10 ) Group Delay Distortion ADC Digital Filter(HPF): Frequency Response (Note 9 ) -3dB -0.5dB -0.1dB DAC Digital Filter: Passband (Note 9 ) -0.06dB -6.0dB
SB PR SA GD GD FR
PB SB PR SA GD
Stopband Passband Ripple Stopband Attenuation Group Delay
(Note 10 )
0.1 FR dB Notes: 9. The Passband and stopband frequencies scale with fs. For example, 20.02kHz at -0.02dB is 0.454 x fs. 10. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 20bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20bit data of both channels on input register to the output of analog signal.
DAC Digital Filter+Analog Filter: Frequency Response 020.0kHz
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ASAHI KASEI
[AK4520A]
DIGITAL CHARACTERISTICS (Ta=25C; VA,VD=2.75.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-100uA) Low-Level Output Voltage (Iout=100uA) Input Leakage Current Symbol VIH VIL VOH VOL Iin min 70%VD VD-0.5 typ max 30%VD 0.5 10 Units V V V V uA
SWITCHING CHARACTERISTICS (Ta=25C; VA,VD=2.75.5V; CL=20pF) Parameter Master Clock Timing 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High VD=2.7-3.6V VD=4.5-5.5V (Note 11 ) Symbol fCLK tCLKL tCLKH fCLK tCLKL tCLKH fs fs min 4.096 27 27 6.144 20 20 16 16 45 289.4 120 120 30 30 100 100 40 40 typ max 13.824 Unit MHz ns ns MHz ns ns kHz % ns ns ns ns ns ns ns ns ns
20.736
LRCK Frequency
44.1 44.1
tPW 150 ns tPWV 516 1/fs Notes: 11.If the duty cycle of LRCK changes larger than 5 to 50%, the AK4520A is reset by the internal phase circuit automatically. 12.SCLK rising edge must not occur at the same time as LRCK edge. 13.These cycles are the number of LRCK rising from PWAD rising.
Duty Cycle Serial Interface Timing SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK "" (Note 12 ) SCLK "" to LRCK Edge (Note 12 ) LRCK to SDTO(MSB) SCLK "" to SDTO SDTI Hold Time SDTI Setup Time Reset Timing PWAD & PWDA Pulse Width PWAD "" to SDTO valid (Note 13 )
50 54 55
tSCK tSCKL tSCKH tLRS tSLR tLRM tSSD tSDH tSDS
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ASAHI KASEI Timing Diagram
[AK4520A]
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ASAHI KASEI
[AK4520A]
OPERATION OVERVIEW System Clock Input The AK4520A with CMODE is used to select either MCLK=256fs or 384fs. The relationship between the external clock applied to the MCLK input and the desired sample rate is defined in Table 1 . The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to LRCK upon power-up or when the internal timing becomes out of phase. All external clocks must be present unless both PWDA and PWAD ="L", otherwise excessive current may result from abnormal operation of internal dynamic logic.
MCLK fs 32.0kHz 44.1kHz 48.0kHz 256fs CMODE="L" 384fs CMODE="H"
SCLK 64fs 32fs 1.0240MHz 1.4112MHz 1.5360MHz
8.1920MHz 12.2880MHz 2.048MHz 11.2896MHz 16.9344MHz 2.822MHz 12.2880MHz 18.4320MHz 3.072MHz Table 1 . System Clock Example
Audio Serial Interface Format Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes are supported selected by the DIF0 and DIF1 pins as shown in Table 2 . In all modes the serial data is MSB-first, 2's compliment format is clocked on the falling edge of SCLK. For mode 3, if SCLK is 32fs, then the least significant bits will be truncated. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO(ADC) 20bit, MSB justified 20bit, MSB justified 20bit, MSB justified IIS(I2S) SDTI(DAC) 16bit, LSB justified 20bit, LSB justified 20bit, MSB justifie IIS(I2S) Table 2 . Serial Data Modes L/R H/L H/L H/L L/H SCLK 32fs 40fs 40fs 32fs or 40fs
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ASAHI KASEI
[AK4520A]
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1997/3
ASAHI KASEI
[AK4520A]
Digital High Pass Filter The ADC of AK4520A has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and also scales with sampling rate(fs). De-emphasis filter The DAC of AK4520A includes the digital de-emphasis filter(tc=50/15us) by IIR filter. This filter corresponds to three frequencies (32kHz,44.1kHz,48kHz). The de-emphasis filter selected by DEM0 and DEM1 is enabled for input audio data. The de-emphasis is also disabled at DEM0="1" and DEM1="0". DEM 1 DEM0 Mode
0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 3 . De-emphasis filter control
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ASAHI KASEI Power-Down & Reset
[AK4520A]
The ADC and DAC of AK4520A are placed in the power-down mode by bringing each power down pin, PWAD PWDA "L" independently and each digital filter is also reset at the same time. This reset should always be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 5 shows the power-up sequence when the DAC is powered up before the ADC power-up.
1 { 2 {
The analog part of ADC is initialized after exiting the power-down state. Digital output corresponding to analog input and analog output corresponding to digital input have the group delay(GD). A/D output is "0" data at the power-down state. Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click noise influences system application. Required muting time depends on the configuration of the input buffer circuits. Figure 6: 1s Figure 9: 200ms Click noise occurs at the edge of PWDA. 5 Please mute the analog output externally if the click noise({ ) influences system application. Figure 5 . Power-up sequence
{ 4 {
3
5 { 6 {
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ASAHI KASEI
[AK4520A]
SYSTEM DESIGN Figure 6 shows the system connection diagram. This is an example which analog signal is input by single ended circuit. In case of differential input, please refer to Figure 9 . An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
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ASAHI KASEI
[AK4520A]
Figure 8 . Power Supply Arrangement
1. Grounding and Power Supply Decoupling The AK4520A requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK4520A should be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4520A as possible, with the small value ceramic capacitor being the nearest.
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ASAHI KASEI 2. On-chip voltage reference
[AK4520A]
The differential Voltage between VREFH and VREFL sets the analog input/output range. VREFH pin is normally connected to VA with a 0.1uF ceramic capacitor and VREFL pin is connected to AGND. VCOM is a signal ground of this chip. An electrolytic capacitor 10uF parallel with a 0.1uF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH,VREFL and VCOM pins in order to avoid unwanted coupling into the AK4520A. 3. Analog Inputs The ADC inputs are differential and internally biased to the common voltage(VA/2) with 30k (typ) resistance. Figure 6 is a circuit example which analog signal is input by single end. the signal can be input from either positive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x (VREFH-VREFL) Vpp. In case of single ended input, the distortion around full scale degrades compared with differential input. Figure 9 is a circuit example which analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and nominally 0.3 x (VREFH-VREFL) Vpp. The AK4520A can accept input voltages from AGND to VA. The ADC output data format is 2's complement The output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input below a negative full scale. The ideal code is 00000H(@20bit) with no input signal. The DC offset is removed by the internal HPF. The AK4520A samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter(fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs. The AK4520A has tone noise with around -110dB on the ADC output. There are two methods of dropping VD to 3V or adding a small DC offset at the ADC input to reduce the noise level. The evaluation board(AKD4520) manual should be referred about the detail.
Figure 9 . Differential Input Buffer Example
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ASAHI KASEI 4. Analog Outputs
[AK4520A]
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.626 x (VREFH-VREFL) Vpp. The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFFH(@20bit) and a negative full scale for 80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). The internal switched-capacitor filter and continuous-time filter removes most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. Figure 10 shows the example of external op-amp circuit with 6dB gain. The output signal is inverted by using the circuit in this case.
Figure 10 . External analog circuit example(gain=6dB)
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ASAHI KASEI
[AK4520A]
PACKAGE
z 28pin VSOP (Unit: mm)
Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
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ASAHI KASEI
[AK4520A]
MARKING
XXXBYYYYC date code identifier XXXB: Lot number(X:Digit number, B:Alpha character) YYYYC: Assembly date(Y:Digit number,C:Alpha character)
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IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. zAKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. zAny export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. zAKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. zIt is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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